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  data sheet the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. bipolar analog integrated circuit m m m m pc8129gr up converter with agc function + quadrature modulator ic for digital mobile communication systems ? 1997, 1999 document no. p12781ej2v0ds00 (2nd edition) date published october 1999 n cp(k) printed in japan data sheet the mark shows major revised points. description the m pc8129gr is a silicon monolithic integrated circuit designed as indirect quadrature modulator for digital mobile communication systems. this modulator consists of 0.8 ghz to 1.9 ghz up-converter and 100 mhz to 400 mhz quadrature modulator which are packaged in 20 pin ssop. the device has power save function and can operate 2.7 to 5.5 v supply voltage, therefore, it can contribute to make rf block small, high performance and low power consumption. features ? high linearity up converter is incorporated; p rfout = C5 dbm typ./@f rfout = 900 mhz ? wide operating frequency range. up converter ; f rfout = 800 mhz to 1900 mhz modulator ; f lo1in = 200 mhz to 800 mhz f modout = 100 mhz to 400 mhz, f i/q = dc to 10 mhz ? external if filter can be applied between modulator output and up converter input terminal. ? low phase difference due to digital phase shifter is adopted. ? supply voltage: v cc = 2.7 to 5.5 v ? equipped with power save function. ? 20 pin ssop suitable for high density surface mounting. applications ? digital cellular phones (ex. gsm etc) ? digital cordless phones ordering information part number package supplying form m pc8129gr-e1 20 pin plastic ssop (225 mil) embossed tape 12 mm wide. qty 2.5 kp/reel. pins 1 through 10 are in pull-out direction. * to order evaluation samples, please contact your local nec sales office. (part number for sample order: m pc8129gr) caution electro-static sensitive device
data sheet p12781ej2v0ds00 2 m m m m pc8129gr internal block diagram and pin connections up-con in up-con inb modout i ib qb q lo1 in lo1 inb gnd 1 2 3 4 5 6 7 8 9 10 v cc (mod) v cc (up-con) rfout gnd v ps v agc gnd lo2 in lo2 inb gnd 20 19 18 17 16 15 14 13 12 11 reg. 90deg. phase shifter ( 2) quadrature modulator series product part number functions i cc (ma) f lo1in (mhz) f modout (mhz) rf mixer f rfout (mhz) phase shifter package application m pc8101gr 150 mhz quad.mod 15/@2.7 v 100 to 300 50 to 150 external f/f ct-2 etc. m pc8104gr rf up-converter + if quad.mod 28/@3.0 v 100 to 400 900 to 1 900 20-pin ssop (225 mil) m pc8105gr 400 mhz quad.mod 16/@3.0 v 100 to 400 external 16-pin ssop (225 mil) digital comm. m pc8110gr 1 ghz direct quad.mod 24/@3.0 v 800 to 1 000 external pdc800 mhz, etc. m pc8125gr rf up-converter + if quad.mod + agc 36/@3.0 v 220 to 270 1 800 to 2 000 phs m pc8126gr 915 to 960 915 to 960 20-pin ssop (225 mil) m pc8126k 900 mhz direct quad.mod with offset-mixer 35/@3.0 v 889 to 960 889 to 960 doubler + f/f 28-pin qfn pdc800 mhz m pc8129gr 2lo if quad. mod+rf up-converter 28/@3.0 v 200 to 800 100 to 400 800 to 1 900 f/f 20-pin ssop (225 mil) gsm, dcs1800, etc. m pc8139gr-7jh transceiver ic (1.9 ghz indirect quad. mod + rx-if + if vco) tx: 32.5 rx: 4.8 /@3.0 v 220 to 270 1 800 to 2 000 30-pin tssop (225 mil) phs m pc8158k rf up-converter + if quad.mod + agc 28/@3.0 v 100 to 300 800 to 1 500 cr 28-pin qfn pdc800 m/1.5 g
data sheet p12781ej2v0ds00 3 m m m m pc8129gr application example [gsm] lna 1st mix sw sub ant sw sw main ant pa tx rx 2nd mix (f/f) f demo. i q pll1 pll2 1st. lo 2nd. lo agc modout = f lo /2 90 f lo 0 i q pc8129gr m
data sheet p12781ej2v0ds00 4 m m m m pc8129gr absolute maximum ratings parameter symbol rating unit condition supply voltage v cc 6.0 v t a = +25 c power save voltage v ps 6.0 v agc control voltage v agc 6.0 v iq dc offset voltage iq (dc) 4.0 v power dissipation p d 430 mw t a = +85 c note operating ambient temperature t a C40 to +85 c storage temperature t stg C55 to +150 c note mounted on double sided copper clad 50 50 1.6 mm epoxy glass pwb. recommended operating conditions parameter symbol min. typ. max. unit conditions supply voltage v cc 2.7 3.0 5.5 v operating ambient temperature t a C40 +25 +85 c up converter rf frequency f rfout 800 1900 mhz up converter input freq. f upconin 100 400 mhz modulator output frequency f modout lo1 input frequency f lo1in 200 800 mhz lo1 input level p lo1in C15 C10 C5 dbm lo2 input frequency f lo2in 800 1800 mhz lo2 input level p lo2in C15 C10 C5 dbm i/q input frequency f i/qin dc 10 mhz i/q input amplitude v i/qin 600 mv p-p single ended input
data sheet p12781ej2v0ds00 5 m m m m pc8129gr electrical characteristics (1) conditions (unless otherwise specified): t a = +25 c, v cc = 3 v, v ps = 3 v, r ps = 1 k w , v agc = 3 v, r agc = 10 k w i/q dc = 1.5 v (vbias(i) = vbias(ib) = vbias (q) = vbias (qb) = 1.5 v) f i/qin = 67.7 khz, v i/qin = 500 mv p-p (single ended input, ib = qb = 0 mv p-p ) modulation pattern: <0000> f lo1in = 500 mhz, p lo1in = C10 dbm f lo2in = 1150 mhz, p lo2in = C10 dbm f upconin = f modout = f lo1in /2 + f i/qin = 250 mhz + f i/qin f rfout = 900 mhz C f i/qin parameter symbol min. typ. max. unit test conditions up converter + quadrature modulator total total circuit current i cc(total) 20 28 37 ma no input signal total circuit current at power save mode i cc(ps)total1 0.6 10 m av ps 0.5 v total output power p rfout C8 C5 C2 dbm local oscillator carrier leakage lol C40 C26.5 dbc f lol = f lo2 C f lo1 /2 image rejection (side band leak) imr C30 C26.5 dbc agc gain control rang gcr 28 40 db v agc = 2.5 v to 0 v power save rise time t ps (rise) 2.0 5.0 m sv ps (low) ? v ps (high) power save fall time t ps (fall) 2.0 5.0 m sv ps (high) ? v ps (low) up converter block circuit current at power save mode i cc(ps) (up con.) 5.0 m av ps 0.5 v quadrature modulator block circuit current at power save mode i cc(ps) (mod) 5.0 m av ps 0.5 v
data sheet p12781ej2v0ds00 6 m m m m pc8129gr standard characteristics for reference (1) conditions (unless otherwise specified): t a = +25 c, v cc = 3 v, v ps = 3 v, r ps = 1 k w , v agc = 3 v, r agc = 10 k w i/q dc = 1.5 v (vbias(i) = vbias(ib) = vbias (q) = vbias (qb) = 1.5 v) f i/qin = 67.7 khz, p i/qin = 500 mv p-p (single ended input, ib = qb = 0 mv p-p ) modulation pattern: <0000> f lo1in = 500 mhz, p lo1in = C10 dbm f lo2in = 1150 mhz, p lo2in = C10 dbm f upconin = f modout = f lo1in /2 + f i/qin = 250 mhz + f i/qin f rfout = 900 mhz C f i/qin parameter symbol reference unit test conditions up converter + quadrature modulator total total circuit current at power-save mode i cc(ps)total2 60 m av ps 0.5 v, v agc = 0 v phase error df 1.8 deg. (rms) mod pattern: pn9 up converter block up con. circuit current i cc(upcon) 14 ma no input signal up con. circuit current at power-save mode i cc(ps)upcon 60 m av ps 0.5 v, v agc = 0 v conversion gain cg 12 db p upconin = C20 dbm maximum output power p rf(sat) C1.5 dbm p upconin = C4 dbm output 3rd order intercept point oip 3 +6 dbm f upconin = 250.0 mhz/250.2 mhz quadrature modulator block mod. circuit current i cc(mod) 14 ma no input signal output power p modout C16.5 dbm lo1 carrier leakage lol C40 dbc f lol = f lo1 /2 image rejection (side band leak) imr C30 dbc i/q 3rd order intermodulation distortion im 3i/q C50 dbc i/q input impedance z i/q 200 k w i to ib, q to qb iq bias current i i/q 5 m a i, ib, q, qb to gnd (each) lo1 input vswr vswr (lo1) 1.2 : 1 C output noise floor C133 dbc/hz d f = 20 mhz
data sheet p12781ej2v0ds00 7 m m m m pc8129gr standard characteristics for reference (2) conditions (unless otherwise specified): t a = +25 c, v cc = 3 v, v ps = 3 v, r ps = 1 k w , v agc = 3 v, r agc = 10 k w i/q dc = 1.5 v (vbias(i) = vbias(ib) = vbias (q) = vbias (qb) = 1.5 v) f i/qin = 67.7 khz, p i/qin = 500 mv p-p (single ended input, ib = qb = 0 mv p-p ) modulation pattern: <0000> f lo1in = 500 mhz, p lo1in = C10 dbm f lo2in = 1650 mhz, p lo2in = C10 dbm f upconin = f modout = f lo1in /2 + f i/qin = 250 mhz + f i/qin f rfout = 1900 mhz + f i/qin parameter symbol reference unit test conditions up converter + quadrature modulator total total output power p rfout C12 dbm local oscillator carrier leakage lol C40 dbc f lol = f lo2 + f lo1 /2 image rejection (side band leak) imr C30 dbc agc gain control rang gcr 45 db v agc = 2.5 v to 0 v phase error df 1.8 deg. (rms) mod pattern: pn9 up converter block conversion gain cg 5 db p upconin = C20 dbm maximum output power p rf(sat) C7 dbm p upconin = C4 dbm output intercept point oip 3 C1 dbm f upconin = 250.0 mhz/250.2 mhz
data sheet p12781ej2v0ds00 8 m m m m pc8129gr 1 2 18 pin explanation pin no. symbol supply voltage (v) pin voltage typ. (v) @v cc = 3 v description equivalent circuit 18 rfout v cc C rf output from up-converter. this pin is open collector output. 1 upcon in C 2.2 if input for up-converter. this pin is high impedance input. 2 upcon inb C 2.2 bypass of if input. grounded through external capacitor. 3 modout C 1.9 output from modulator. this is emitter follower output. 4iv cc /2 C input for i signal. this input impedance is about 200 k w . relations between amplitude and v cc /2 bias of input signal are following. 5ibv cc /2 C input for i signal. this input impedance is about 200 k w . v cc /2 biased dc signal should be input. 6qbv cc /2 C input for q signal. this input impedance is about 200 k w v cc /2 biased dc signal should be input. 7qv cc /2 C input for q signal. this input impedance is about 200 k w . relations between amplitude and v cc /2 bias of input signal are following. note in the case of that i/q input signals are single ended. of course, i/q signal inputs can be used either single endedly or differentially with proper terminations. note v cc /2 (v) signal level (mv p-p ) 3 1.35 400 3 1.5 600 3 1.75 1000 v cc /2 (v) signal level (mv p-p ) 3 1.35 400 3 1.5 600 3 1.75 1000 note 3 4 5 6 7
data sheet p12781ej2v0ds00 9 m m m m pc8129gr pin explanation pin no. symbol supply voltage (v) pin voltage typ. (v) @v cc = 3 v description equivalent circuit 8 lo1in C 0 lo1 input for phase shifter. this input impedance is 50 w matched internally. 9 lo1in b C 2.3 bypass of lo1 input. this pin is grounded through internal capacitor. 10 11 gnd for modulator 0 C connect to the ground with minimum inductance. track length should be kept as short as possible. 12 lo2in b C 1.9 bypass of lo2 input. grounded through external capacitor. 13 lo2in C 1.9 lo2 input of up-converter. this pin is high impedance input. 14 17 gnd for up-con. 0 C connect to the ground with minimum inductance. track length should be kept as short as possible. 15 v agc 0 to v cc C input for agc amplifier. total output power can be controlled by changing input voltage. and as external series resistance (r agc ) connecting, a slope of agc curve can be changed by the resistance (r agc ). 16 power save 0 to v cc C power save control pin can be controlled on/off state with bias as follows; 19 v cc for up- converter 2.7 to 5.5 C supply voltage pin for up- converter. 20 v cc for modulator 2.7 to 5.5 C supply voltage pin for modulator. internal regulator can be kept stable condition of supply bias against the variable temperature or v cc . : externally v ps (v) state 2 to v cc on (active mode) 0 to 0.5 off (sleep mode) 50 w 9 8 12 13 16
data sheet p12781ej2v0ds00 10 m m m m pc8129gr standard typical characteristics test circuit 1, t a = +25 c, v cc = 3 v, v ps = 3 v, r ps = 1 k w , v agc = 3 v, r agc = 10 k w i/q dc = 1.5 v (vbias(i) = vbias(ib) = vbias(q) = vbias(qb) = 1.5 v) f i/qin = 67.7 khz, v i/qin = 500 mv p-p (single ended input, ib = qb = 0 mv p-p ) modulation pattern: all zero <0000>, f lo1in = 500 mhz, p lo1in = C10 dbm f lo2in = 1150 mhz, p lo2in = C10 dbm, f upconin = f modout = f lo1in /2 + f i/qin = 250 mhz + f i/qin f rfout = 900 mhz C f i/qin , unless otherwise specified i cc (total) vs v cc v cc - supply voltage - v i cc - total circuit current - ma i cc (total) vs v ps v ps - power save control voltage - v i cc - total circuit current - ma i cc (total) vs t a t a - operating ambient temperature - c i cc - total circuit current - ma i cc (ps) total vs t a t a - operating ambient temperature - c i cc - total circuit current at power save mode - a m 40 30 20 10 0 no input signal 0123456 30 20 10 0 0123 t a = +25 c t a = +85 c t a = ?0 c : : : no input signal 30 20 10 0 ?0 ?0 0 +20 +40 +60 +80 no input signal 30 20 10 0 ?0 ?0 0 +20 +40 +60 +80 no input signal vps = 0.5 v
data sheet p12781ej2v0ds00 11 m m m m pc8129gr i cc - total circuit current at power save mode - a m i cc - total circuit current at power save mode - a m i cc (ps) total1 vs v cc v cc - supply voltage - v i cc (ps) total2 vs v cc v cc - supply voltage - v p rfout , lol, imr, im 3i/q vs v cc v cc - supply voltage - v p rfout - total output power - dbm lol - local oscillator carrier leakage - dbc imr - image rejection - dbc im 3i/q - i/q 3rd order intermodulation distortion - dbc lol - local oscillator carrier leakage - dbc imr - image rejection - dbc im 3i/q - i/q 3rd order intermodulation distortion - dbc p rfout , lol, imr, im 3i/q vs t a t a - operating ambient temperature - c p rfout - total output power - dbm i cc (ps) total2 vs t a t a - operating ambient temperature - c i cc - total circuit current at power save mode - a m 0 ?0 25 50 75 100 125 150 ?0 0 +20 +40 +60 +80 no input signal vps = 0.5 v v agc = 0 v 2 1 0 0246 no input signal vps = 0.5 v 0 25 50 75 100 125 150 0246 no input signal vps = 0.5 v v agc = 0 v lol im 3i/q p rfout imr 0 ?0 ?0 ?0 0123456 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 0 +20 +40 +60 +80 ?0 ?0 ?0 ?0 p rfout imr lol im 3i/q
data sheet p12781ej2v0ds00 12 m m m m pc8129gr p rfout , lol, imr, im 3i/q vs v i/qin v i/qin - i/q input amplitude - mvp-p p rfout - total output power - dbm p rfout , lol, imr, im 3i/q vs p lo1in p lo1in - lo1 input level - dbm p rfout vs p lo2in p lo2in - lo2 input level - dbm p rfout - total output power - dbm vs v i/qin v i/qin - i/q input amplitude - mv p-p - phase error - deg. (rms.) p rfout vs v agc v agc - agc control voltage - v p rfout - total output power - dbm p rfout vs v agc v agc - agc control voltage - v p rfout - total output power - dbm lol - local oscillator carrier leakage - dbc imr - image rejection - dbc im 3i/o - i/q 3rd order intermodulation distortion - dbc lol - local oscillator carrier leakage - dbc imr - image rejection - dbc im 3i/o - i/q 3rd order intermodulation distortion - dbc 0 ?0 ?0 ?0 ?0 100 500 1000 2000 ?0 ?0 ?0 ?0 ?0 ?0 p rfout - total output power - dbm lol im 3i/q p rfout imr p rfout imr lol im 3i/q ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 +10 0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 df df 0 1 2 3 4 5 6 7 100 500 1000 mod pattern: pn9 +10 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 023 1 t a = +85 c +25 c ?0 c gcr = 40.8 db (v cc = 3 v) gcr = 40.5 db (v cc = 2.7 v) gcr = 41.7 db (v cc = 5.5 v) v cc = 2.7 v v cc = 3 v v cc = 5.5 v 0 ?0 ?0 ?0 ?0 ?0 ?0 023 1456
data sheet p12781ej2v0ds00 13 m m m m pc8129gr p rfout vs v agc v agc - agc control voltage - v p rfout - total output power - dbm power save response typical sine wave modulation output spectrum typical gmsk modulation output spectrum typical sine wave modulation output spectrum typical sine wave modulation output spectrum (in band) ?0 0 ?0 ?0 ?0 ?0 ?0 0 +10 123 r agc = 80 k w , slope = 53 db/v r agc = 10 k w , slope = 143 db/v gcr = 39.8 db att 10db rbw 3 mhz vbw 3 mhz swp 50 s m center 900.0677 mhz span 0 hz pc8129gr ref 0.0 dbm 10 db/ m att 10 db rbw 3 khz vbw 10 khz swp 1.0 s center 900.0000 mhz span 500 khz pc8129gr ref 0.0 dbm 10 db/ m 1 3 no.1: no.2: no.3: no.4: 899.9323 mhz 900.0000 mhz 900.0677 mhz 900.2031 mhz ?.80 dbm ?8.02 dbc ?9.88 dbc ?2.41 dbc *** multi marker list *** att 0 db rbw 3 khz vbw 10 khz swp 5.0 s center 900. 000 mhz span 2.000 mhz pc8129gr ref ?0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: no.5: no.6: d : 899.200 mhz 899.400 mhz 899.600 mhz 900.400 mhz 900.600 mhz 900.800 mhz ?7.25 db ?6.50 db ?8.00 db ?8.25 db ?7.50 db ?7.50 db *** multi marker list *** dl ?0.0 dbm adj bs 135 khz marker 899.200 mhz ?7.25 db a write b view att 10 db rbw 300 khz vbw 300 khz swp 5.0 s start 0 hz stop 2.460 ghz pc8129gr ref 0.0 dbm 10 db/ m marker 900 mhz ?.67 dbm f lo1in (= f if ) 2 1 f lo1in (= 2f if ) f lo1in (= 3f if ) 2 3 2 f lo1in (= 4f if ) f lo1in (= 5f if ) 2 5 f lo2in att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 900.0 mhz span 400.0 mhz pc8129gr ref 0.0 dbm 10 db/ m marker 900 mhz ?.68 dbm mkr 900 mhz 750 mhz ?3.6 dbm 800 mhz ?9.5 dbm 850 mhz ?6.6 dbm 950 mhz ?8.2 dbm 1000 mhz ?3.0 dbm 1050 mhz ?9.4 dbm 2 4 1 2 3 4 5 6
data sheet p12781ej2v0ds00 14 m m m m pc8129gr typical sine wave modulation output spectrum (in band) typical sine wave modulation output spectrum (in band) typical sine wave modulation output spectrum (in band) att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 920.0 mhz span 200.0 mhz pc8129gr ref 0.0 dbm 10 db/ m marker 880.0 mhz ?.64 dbm 870 mhz ?5.7 dbm 890 mhz ?3.0 dbm 1000 mhz ?4.8 dbm 1010 mhz ?7.6 dbm f lo1in = 500 mhz (f modout = 250 mhz + f i/q ) f lo2 = 1130 mhz f rfout = 880 mhz att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 920.0 mhz span 200.0 mhz pc8129gr ref 0.0 dbm 10 db/ m marker 900 mhz ?.66 dbm 850 mhz ?6.2 dbm 950 mhz ?5.5 dbm 1000 mhz ?3.0 dbm mkr 900 mhz att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 920.0 mhz span 200.0 mhz pc8129gr ref 0.0 dbm 10 db/ m marker 900 mhz ?.41 dbm f lo1in = 500 mhz (f modout = 250 mhz + f i/qin ) f lo2in = 1210 mhz f rfout = 960 mhz ?f i/qin mkr 900 mhz 880 mhz ?9.9 dbm 920 mhz ?1.5 dbm 1000 mhz ?9.9 dbm
data sheet p12781ej2v0ds00 15 m m m m pc8129gr standard typical characteristics test circuit 2, t a = +25 c, v cc = 3 v, v ps = 3 v, r ps = 1 k w , v agc = 3 v, r agc = 10 k w i/q dc = 1.5 v (vbias(i) = vbias(ib) = vbias(q) = vbias(qb) = 1.5 v) f i/qin = 67.7 khz, v i/qin = 500 mv p-p (single ended input, ib = qb = 0 mv p-p ) modulation pattern: all zero <0000>, f lo1in = 500 mhz, p lo1in = C10 dbm f lo2in = 500 mhz, p lo2in = C10 dbm, f upconin = f modout = f lo1in /2 + f i/qin = 250 mhz + f i/qin f rfout = 1900 mhz + f i/qin , unless otherwise specified p rfout vs v agc v agc - agc control voltage - v p rfout - total output power - dbm p rfout vs v i/qin v i/qin - i/q input amplitude - mv p-p p rfout - total output power - dbm p rfout vs p lo1in p lo1in - lo1 input level - dbm p rfout - total output power - dbm p rfout vs p lo2in p lo2in - lo2 input level - dbm p rfout - total output power - dbm r agc = 80 k w , slope = 59 db/v r agc = 10 k w , slope = 154 db/v gcr = 45.4 db ?0 0 ?0 ?0 ?0 ?0 ?0 123 ?0 0 ?0 ?0 ?0 ?0 0 100 500 1000 2000 ?0 ?0 ?0 0 ?0 ?0 ?0 0 +10 ?0 ?0 ?0 0 ?0 ?0 ?0 0 +10 ?0
data sheet p12781ej2v0ds00 16 m m m m pc8129gr f - phase error - deg. (rms) d f vs v i/qin d v i/qin - i/q input amplitude - mvp-p typical sine wave modulation output spectrum typical gmsk modulation output spectrum typical sine wave modulation output spectrum typical sine wave modulation output spectrum (in band) typical sine wave modulation output spectrum (in band) 0 100 1 2 3 4 5 6 7 500 1000 2000 rbw 300 khz vbw 300 khz swp 5.0 s start 0 hz stop 2.500 ghz pc8129gr ref 0.0 dbm 10 db/ m marker 1.900 ghz ?1. 67 dbm mkr 1.900 ghz att 10 db f lo1in (= f if ) 2 1 f lo1in (= 2f if ) f lo1in (= 3f if ) 2 f lo1in (= 4f if ) 2 3 f lo1in (= 5f if ) 2 5 3 f lo1in (= 6f if ) f lo1in (= 7f if ) 2 7 4 f lo1in (= 8f if ) f lo2in att 0 db rbw 3 khz vbw 10 khz swp 5.0 s center 1.900000 ghz span 2. 000 mhz pc8129gr ref ?0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: no.5: no.6: d : 1.899200 ghz 1.899400 ghz 1.899600 ghz 1.900400 ghz 1.900600 ghz 1.900800 ghz ?4.75 db ?4.50 db ?4.75 db ?6.50 db ?4.25 db ?4.75 db *** multi marker list *** dl ?0.0 dbm mkr 1.899200 ghz marker 1. 899200 ghz ?4. 75 db a write b view 1 3 att 10 db rbw 3 khz vbw 10 khz swp 1.0 s center 1.9000000 ghz span 500 khz pc8129gr ref 0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: 1.9000677 ghz 1.9000000 ghz 1.8999323 ghz 1.8997969 ghz ?2.13 dbm ?9.30 dbc ?8.98 dbc ?1.30 dbc *** multi marker list *** 3 4 5 6 7 att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 1.9000 ghz span 600 mhz pc8129gr ref 0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: no.5: no.6: no.7: 1.900 ghz 1.650 ghz 1.750 ghz 1.800 ghz 2.000 ghz 2.050 ghz 2.150 ghz ?1.71 dbm ?4.07 dbm ?4.52 dbm ?3.37 dbm ?1.09 dbm ?9.39 dbm ?1.62 dbm *** multi marker list *** 1 7 att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 1.7950 ghz span 600 mhz pc8129gr ref 0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: no.5: no.6: no.7: 1.710 ghz 1.670 ghz 1.750 ghz 1.920 ghz 1.940 ghz 1.960 ghz 2.000 ghz ?5.16 dbm ?1.50 dbm ?7.84 dbm ?6.33 dbm ?8.68 dbm ?7.94 dbm ?2.11 dbm *** multi marker list *** f rfout = 1.71 ghz + f i/qin f lo2in = 1.46 ghz mod pattern: pn9 4 2 1 2 3 5 4 6 2 2 3 4 1 5 6
data sheet p12781ej2v0ds00 17 m m m m pc8129gr typical sine wave modulation output spectrum (in band) typical sine wave modulation output spectrum (in band) 2 5 6 att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 1.7950 ghz span 600 mhz pc8129gr ref 0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: no.5: no.6: no.7: 1.795 ghz 1.545 ghz 1.590 ghz 1.750 ghz 1.840 ghz 2.000 ghz 2.045 ghz ?4.21 dbm ?4.47 dbm ?5.96 dbm ?6.40 dbm ?0.91 dbm ?1.79 dbm ?8.73 dbm *** multi marker list *** f rfout = 1.795 ghz + f i/qin f lo2in = 1.545 ghz 1 2 3 4 5 6 att 10 db rbw 300 khz vbw 300 khz swp 5.0 s center 1.7950 ghz span 600 mhz pc8129gr ref 0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: no.5: no.6: 1.880 ghz 1.630 ghz 1.750 ghz 1.760 ghz 2.000 ghz 2.010 ghz ?2.32 dbm ?3.47 dbm ?4.08 dbm ?3.19 dbm ?1.05 dbm ?0.25 dbm *** multi marker list *** f rfout = 1.88 ghz + f i/qin f lo2in = 1.63 ghz 1 3 4 7
data sheet p12781ej2v0ds00 18 m m m m pc8129gr standard typical characteristics t a = +25 c, v cc = 3.0 v, v ps = 3.0 v, f upconin = 250 mhz, p upconin = C20 dbm test circuit 1 (f rfout = 900 mhz, f lo2in = 1150 mhz) or test circuit 2 (f rfout = 1900 mhz, f lo2in = 1650 mhz), unless otherwise specified p rfout - output power - dbm im 3 - 3rd order intermoduration distortion - dbm p rfout , im 3 , vs p upconin p upconin - up-converter input level - dbm p rfout - output power - dbm im 3 - 3rd order intermoduration distortion - dbm p rfout , im 3 , vs p upconin p upconin - up-converter input level - dbm cg vs p lo2in p lo2in - lo2 input level - dbm cg - conversion gain - db f upconin = 250.0/250.2 mhz f lo2in = 1.15 ghz f rfout = 899.8/900.0 mhz p rfout im 3 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 0 oip 3 = +5.8 dbm f upconin = 250.0/250.2 mhz f lo2in = 1.65 ghz f rfout = 1.9000/1.9002 ghz p rfout im 3 oip 3 = ?.3 dbm ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 ?0 0 ?0 f rfout = 900 mhz f lo2in = 1.15 ghz f rfout = 1.9 ghz f lo2in = 1.65 ghz 0 5 10 15 ?0 ?0 ?0 ?0 0
data sheet p12781ej2v0ds00 19 m m m m pc8129gr standard typical characteristics test circuit 1 or 2, t a = +25 c, v cc = 3 v, v ps = 3 v i/q dc = 1.5 v (vbias(i) = vbias(ib) = vbias(q) = vbias(qb) = 1.5 v) f i/qin = 67.7 khz, v i/qin = 500 mv p-p (single ended input, ib = qb = 0 mv p-p ) modulation pattern: all zero <0000>, f lo1in = 500 mhz, p lo1in = C10 dbm f modout = f lo1in /2 + f i/qin = 250 mhz + f i/qin , unless otherwise specified v i/qin - i/q input amplitude - mv p-p - phase error - deg. (rms.) df vs v i/qin df p modout vs v i/qin v i/qin - i/q input amplitude - mv p-p p modout - moduration output power - dbm p modout vs p lo1in p lo1in - lo1 input level - dbm p modout - moduration output power - dbm p modout , lol, imr, im 3i/q vs f lo1in f lo1in - lo1 input frequency - mhz p modout - moduration output power - dbm ?0 ?0 ?0 ?0 ?0 0 +10 ?0 ?0 ?0 ?0 ?0 ?0 +10 ?0 ?0 ?0 0 0 lol - local oscillator carrier leakage - dbc imr - image rejection - dbc im 3i/q - i/q 3rd order intermodulation distortion - dbc p rfout lol imr im 3i/q ?0 ?0 ?0 ?0 ?0 0 100 200 500 2000 ?0 ?0 ?0 ?0 ?0 ?0 1 2 3 100 500 1000 2000 mod pattern: pn9 1000 200 100 200 500 2000 1000
data sheet p12781ej2v0ds00 20 m m m m pc8129gr f lo1in - lo1 input frequency - mhz f - phase error - deg. (rms.) f vs f lo1in typical sine wave modulation output spectrum d d 1 100 0 2 3 4 5 6 7 200 500 2 3 4 1 att 10 db rbw 3 khz vbw 10 khz swp 1.0 s center 250.0000 mhz span 500 kmhz pc8129gr ref 0.0 dbm 10 db/ m no.1: no.2: no.3: no.4: 250.0677 mhz 250.0000 mhz 249.9323 mhz 249.7969 mhz C16.37 dbm C39.49 dbc C31.07 dbc C58.80 dbc *** multi marker list *** mod pattern: pn9 1000 2000
data sheet p12781ej2v0ds00 21 m m m m pc8129gr lo1 input (pin8) impedance v cc = v ps = 3 v mod output (pin3) impedance v cc = v ps = 3 v up-con. input (pin1) impedance v cc = v ps = 3 v lo2 input (pin13) impedance v cc = v ps = 3 v rf output (pin18) impedance v cc = v ps = 3 v ch1 s 11 1 u fs 2: 47.998 w 0.8066 w 256.76 ph 500.000 000 mhz 2 3 1 marker 2 500 mhz marker 1: 2: 3: 200 mhz 500 mhz 800 mhz start 100.000 000 mhz stop 1 000.000 000 mhz ch1 s 22 1 u fs 2: 31.195 w 14.908 w 9.4909 nh 250.000 000 mhz marker 2 250 mhz marker 1: 2: 3: 100 mhz 250 mhz 400 mhz start 50.000 000 mhz stop 500.000 000 mhz ch1 s 11 1 u fs 1: 22.379 w ?3.543 w 1.8905 pf 900.000 000 mhz marker 1 900 mhz marker 1: 2: 3: 900 mhz 1150 mhz 1900 mhz start 800.000 000 mhz stop 2 000.000 000 mhz ch1 s 11 1 u fs 2: 101.78 w ?87.03 w 1.6449 pf 250. 000 000 mhz marker 2 250 mhz marker 1: 2: 3: 100 mhz 250 mhz 400 mhz start 50.000 000 mhz stop 500.000 000 mhz ch1 s 22 1 u fs 1: 18.953 w ?58.83 w 1.1134 pf 900.000 000 mhz marker 1 900 mhz marker 1: 2: 3: 900 mhz 1150 mhz 1900 mhz start 800.000 000 mhz stop 2 000.000 000 mhz 2 1 3 2 3 1 3 2 1 3 2 1 connect to inductor (l 2 = 100 nh) between pin18 and pin19
data sheet p12781ej2v0ds00 22 m m m m pc8129gr test circuit 1 (in the case of f rfout = 900 mhz band) 1 2 3 4 5 6 7 8 9 10 up-con. in up-con. inb modout i ib qb q lo1in lo1inb gnd i(dc), v iin ib(dc) 1000 pf 100 pf 100 pf qb(dc) 1000 pf q(dc), v qin lo1in 100 pf (open) 20 19 18 17 16 15 14 13 12 11 v cc (mod.) v cc (up-con.) rfout gnd v ps v agc gnd lo2in lo2inb gnd vps v cc 1000 pf v cc 1000 pf f rfout z l = 50 w 15 nh 6 pf 84 nh 100 pf r ps = 1 k w v agc r agc = 10 k w lo2in z l = 50 w 6.8 nh 4 pf 100 pf note 1 100 pf note 2 10 nf 10 nf 10 nf 10 nf 10 nf 10 nf notes 1. 50 w matching circuit at f lo2in = 1150 mhz. in the case of using necs evaluation board. 2. 50 w matching circuit at f rfout = 900 mhz. in the case of using necs evaluation board.
data sheet p12781ej2v0ds00 23 m m m m pc8129gr test circuit 2 (in the case of f rfout = 1900 mhz band) 1 2 3 4 5 6 7 8 9 10 up-con. in up-con. inb modout i ib qb q lo1in lo1inb gnd i(dc), v iin ib(dc) 1000 pf 100 pf 100 pf qb(dc) 1000 pf q(dc), v qin lo1in 100 pf (open) 20 19 18 17 16 15 14 13 12 11 v cc (mod.) v cc (up-con.) rfout gnd v ps v agc gnd lo2in lo2inb gnd vps v cc 1000 pf v cc 1000 pf f rfout z l = 50 w 3 pf 68 nh 100 pf r ps = 1 k w v agc r agc = 10 k w lo2in z l = 50 w 2 pf 100 pf note 1 100 pf note 2 10 nf 10 nf 10 nf 10 nf 10 nf 10 nf notes 1. 50 w matching circuit at f lo2in = 1650 mhz. in the case of using necs evaluation board. 2. 50 w matching circuit at f rfout = 1900 mhz. in the case of using necs evaluation board.
data sheet p12781ej2v0ds00 24 m m m m pc8129gr example of test circuit 1 assembled on evaluation board ib qb c = 10 nf c = 10 nf c = 1000 pf c = 100 pf c = 100 pf c = 4 pf c = 100 pf c = 100 pf v agc v ps v cc c = 10 nf c = 10 nf c = 10 nf c = 10 nf c = 10 nf f lo1in = 500 mhz (f modout = 250 mhz + f i/qin ) f lo2in = 1150 mhz f rfout = 900 mhz c = 1000 pf l = 15 nh l = 6.8 nh c = 100 pf c = 100 pf c = 1000 pf l = 84 nh c = 6 pf r ps = 1 k w r agc = 10 k w notes 1. double-sided patterning with 35 m m thick copper on 50 50 0.4 mm polyimide board. 2. gnd pattern on backside. 3. solder coating over patterns. 4. , indicate through-holes. notice the test circuits and board pattern on data sheet are for performance evaluation use only. in the case of actual design-in, matching circuit should be determined using s-parameter of desired frequency in accordance to actual mounting pattern.
data sheet p12781ej2v0ds00 25 m m m m pc8129gr example of test circuit 2 assembled on evaluation board ib qb c = 1000 pf c = 1000 pf c = 100 pf c = 1000 pf c = 3 pf c = 100 pf c = 100 pf c = 2 pf c = 100 pf c = 100 pf v agc v ps v cc c = 10 nf c = 10 nf c = 10 nf c = 10 nf c = 10 nf f lo1in = 500 mhz (f modout = 250 mhz + f i/qin ) f lo2in = 1.65 ghz f rfout = 1.9 ghz + f i/qin c = 100 pf r ps = 1 k w r agc = 10 k w c = 1000 pf l = 68 nh notes 1. double-sided patterning with 35 m m thick copper on polyimide board. 2. gnd pattern on backside. 3. solder coating over patterns. 4. , indicate through-holes. notice the test circuits and board pattern on data sheet are for performance evaluation use only. in the case of actual design-in, matching circuit should be determined using s-parameter of desired frequency in accordance to actual mounting pattern.
data sheet p12781ej2v0ds00 26 m m m m pc8129gr package dimensions 20 pin plastic ssop (225 mil) (unit: mm) 20 detail of lead end 1.8 max. 3 +7 C3 0.65 0.10 m 0.15 0.5 0.2 11 110 6.7 0.3 1.5 0.1 0.1 0.1 0.22 +0.10 C0.05 0.575 max. 0.15 +0.10 C0.05 6.4 0.2 4.4 0.1 1.0 0.2 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition.
data sheet p12781ej2v0ds00 27 m m m m pc8129gr note on correct use (1) observe precautions for handling because of electrostatic sensitive devices. (2) form a ground pattern as widely as possible to minimize ground impedance (to prevent undesired oscillation). (3) keep the track length of the ground pins as short as possible. (4) connect a bypass capacitor (e.x. 1000 pf) to the v cc pin. recommended soldering conditions this product should be soldered in the following recommended conditions. other soldering method and conditions than the recommended conditions are to be consulted with sales representatives. m m m m pc8129gr soldering process soldering conditions symbol infrared ray reflow peak packages surface temperature: 235 c or below, reflow time: 30 seconds or below (210 c or higher) number of reflow process: 2, exposure limit note : none ir35-00-2 vps peak packages surface temperature: 215 c or below, reflow time: 40 seconds or below (200 c or higher) number of reflow process: 2, exposure limit note : none vp15-00-2 wave soldering solder temperature: 260 c or below, flow time: 10 seconds or below, number of flow process: 1, exposure limit note : none ws60-00-1 partial heating method terminal temperature: 300 c or below, flow time: 3 seconds/pin or below, exposure limit note : none note exposure limit before soldering after dry-pack package is opened. storage conditions: 25 c and relative humidity at 65 % or less. caution apply only a single process at once, except for partial heating method. for details of recommended soldering conditions for surface mounting, refer to information document semiconductor device mounting technology manual (c10535e).
m m m m pc8129gr the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8


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